One of the best known test methods for testing large scale integrated circuits is level sensitive scan design (LSSD) which is described in the article "A Logic Design Structure for LSI Testability" Proceedings of the Design Automation Conference, No. 14, 20-22, June 1977, New Orleans, La., by E. B. Eichelberger. See also U.S. Pat. No 4,519,078, U.S. Pat. No. 4,428,060 and E. J. McCluskey, "A Survey of Design for Testability Scan Techniques", VLSI Design, December 1984, pp. 38/61, for a comprehensive list of patents and publications for the testing of electronic structures.
Basically, LSSD utilizes a plurality of controllability/observability points internal to an LSI circuit. Controllability is provided by allowing data to be shifted into these points which are comprised of shift register latches (SRL's) in a serial manner. A test is then performed. The data stored in the SRL's is subsequently shifted back out for observation thereof. Therefore, control/observation of an LSI circuit does not depend on the number of pins in the package. Furthermore, because the latches themselves are part of the internal circuit, they can be utilized to break feedback paths in a sequential circuit, enabling the test for combinational circuits between SRL's to be generated automatically.
In a typical scan design, the shift registers are located at specific points required for the design function but are connected together in the scan chain for testing purposes. The scan chain allows for realization of any test state in the registers for test application. A test pattern is then generated on a computer. The generated test pattern is then shifted into the SRL's, test vectors (selected words or groups of digital data) applied to the primary inputs or pins of the chip, the system clocks applied to perform the test, the primary output pins compared to expected vector outputs and data scanned out of the SRL's to compare it to known good test vectors. In performing this test, numerous series of test vectors are usually required for shifting into the SRL's, applying the test vectors and then shifting the results back out. It is thus seen that in order to fully realize the potential of LSSD testing, test generation software must be able to generate the required test patterns for loading into the SRL's inside the chip. Even though this prior art method is suitable for testing individual IC chips, it does not provide for testing of connections between chips.
In IBM Technical Disclosure Bulletin, Volume 34, No. 6, November 1991, pp. 325-330, by P. K. Graham an AC interconnect test with series boundary scan is described. If an interconnection between two IC chips is to be tested according to this method, first an enable signal is applied to the corresponding driver. After the enabled driver switched on, a receiver clock is pulsed to capture the initialization values into the receiver latches. Only at this point, the timed portion begins. The A-clock of the system is pulsed to the driver data latch. Then, in a minimal, worst-case time after the A-clock, the receiver clock is pulsed to capture the driver data transitions in the receiver boundary latches. This is the end of the timed portion. Thus this prior art test method does not provide for an interconnect test that simulates system operation in the functional mode.
It is thus an object of the present invention to provide an IC chip having improved AC interconnect capability and to provide an improved AC interconnect test method.
According to the above cited prior art and especially according to the above cited Technical Disclosure Bulletin by P. K. Graham the enabling of a driver is not part of the timed portion of the functional or AC interconnect test. In the prior art it is considered to be sufficient to trigger and capture driver transitions between the two binary states once the driver is enabled in order to test the dynamic characteristics of the data transmission between two IC chips.